FPGA_module/uart/uart_tx.v

module uart_tx (
    input  wire       clk,
    input  wire       rstn,
    input  wire       en,
    input  wire       tx_req_start,
    input  wire[7:0]  tx_data,
    output reg        tx_ply_ok,
    output reg        tx_busy,
    output reg        tx_pin
);

parameter DIV = 50;
parameter COUNT_WITH = 6;
reg [COUNT_WITH-1:0] count;

reg [7:0] data_reg;
reg [3:0] tx_count;
reg[2:0] state;

always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        tx_pin <= 1'b1;
        count <= 0;
        tx_count <= 0;
        state <= 0;
        data_reg <= 0;
        tx_ply_ok <= 0;
    end else begin
        if (en == 0) begin
            tx_pin <= 1'b1;
            count <= 0;
            tx_count <= 0;
            state <= 0;
            data_reg <= 0;
            tx_ply_ok <= 0;
        end else begin
            case (state)
                0: begin
                    if (tx_req_start) begin
                        data_reg <= tx_data;
                        state <= 1;
                    end
                    tx_ply_ok <= 0;
                    tx_pin <= 1'b1;
                    tx_count <= 0;
                end
                1: begin
                    tx_ply_ok <= 1'b1;
                    tx_pin <= 1'b0;
                    tx_count <= 1'b0;
                    if(count == DIV-1) begin
                        state <= 2;
                        count <= 0;
                        
                    end else begin
                        count <= count + 1'd1;
                    end
                end
                2: begin
                    tx_ply_ok <= 1'b0;
                    tx_pin <= data_reg[tx_count];
                    if(count == DIV-1) begin
                        count <= 0;
                        tx_count <= tx_count + 1'd1;
                    end else begin
                        count <= count + 1'd1;
                    end
                    if(tx_count == 8) begin
                        state <= 3;
                        tx_pin <= 1'b1;
                    end
                end
                3: begin
                    if(count == DIV-1) begin
                        count <= 0;
                        state <= 0;
                    end else begin
                        count <= count + 1'd1;
                    end
                end
            endcase
        end
    end
end


endmodule