FPGA_module/uart/par/db/excute.hier_info

|uart_top
clk => clk.IN2
rstn => rstn.IN2
rx_pin => rx_pin.IN1
tx_pin << uart_tx:uart_tx_c0.tx_pin


|uart_top|uart_tx:uart_tx_c0
clk => tx_ply_ok~reg0.CLK
clk => data_reg[0].CLK
clk => data_reg[1].CLK
clk => data_reg[2].CLK
clk => data_reg[3].CLK
clk => data_reg[4].CLK
clk => data_reg[5].CLK
clk => data_reg[6].CLK
clk => data_reg[7].CLK
clk => tx_count[0].CLK
clk => tx_count[1].CLK
clk => tx_count[2].CLK
clk => tx_count[3].CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => count[5].CLK
clk => tx_pin~reg0.CLK
clk => state~5.DATAIN
rstn => tx_ply_ok~reg0.ACLR
rstn => data_reg[0].ACLR
rstn => data_reg[1].ACLR
rstn => data_reg[2].ACLR
rstn => data_reg[3].ACLR
rstn => data_reg[4].ACLR
rstn => data_reg[5].ACLR
rstn => data_reg[6].ACLR
rstn => data_reg[7].ACLR
rstn => tx_count[0].ACLR
rstn => tx_count[1].ACLR
rstn => tx_count[2].ACLR
rstn => tx_count[3].ACLR
rstn => count[0].ACLR
rstn => count[1].ACLR
rstn => count[2].ACLR
rstn => count[3].ACLR
rstn => count[4].ACLR
rstn => count[5].ACLR
rstn => tx_pin~reg0.PRESET
rstn => state~7.DATAIN
en => tx_pin.OUTPUTSELECT
en => count.OUTPUTSELECT
en => count.OUTPUTSELECT
en => count.OUTPUTSELECT
en => count.OUTPUTSELECT
en => count.OUTPUTSELECT
en => count.OUTPUTSELECT
en => tx_count.OUTPUTSELECT
en => tx_count.OUTPUTSELECT
en => tx_count.OUTPUTSELECT
en => tx_count.OUTPUTSELECT
en => state.OUTPUTSELECT
en => state.OUTPUTSELECT
en => state.OUTPUTSELECT
en => state.OUTPUTSELECT
en => data_reg.OUTPUTSELECT
en => data_reg.OUTPUTSELECT
en => data_reg.OUTPUTSELECT
en => data_reg.OUTPUTSELECT
en => data_reg.OUTPUTSELECT
en => data_reg.OUTPUTSELECT
en => data_reg.OUTPUTSELECT
en => data_reg.OUTPUTSELECT
en => tx_ply_ok.OUTPUTSELECT
tx_req_start => data_reg.OUTPUTSELECT
tx_req_start => data_reg.OUTPUTSELECT
tx_req_start => data_reg.OUTPUTSELECT
tx_req_start => data_reg.OUTPUTSELECT
tx_req_start => data_reg.OUTPUTSELECT
tx_req_start => data_reg.OUTPUTSELECT
tx_req_start => data_reg.OUTPUTSELECT
tx_req_start => data_reg.OUTPUTSELECT
tx_req_start => state.OUTPUTSELECT
tx_req_start => state.OUTPUTSELECT
tx_req_start => state.OUTPUTSELECT
tx_req_start => state.OUTPUTSELECT
tx_data[0] => data_reg.DATAB
tx_data[1] => data_reg.DATAB
tx_data[2] => data_reg.DATAB
tx_data[3] => data_reg.DATAB
tx_data[4] => data_reg.DATAB
tx_data[5] => data_reg.DATAB
tx_data[6] => data_reg.DATAB
tx_data[7] => data_reg.DATAB
tx_ply_ok <= tx_ply_ok~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_busy <= <GND>
tx_pin <= tx_pin~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_top|uart_rx:uart_rx_c0
clk => rx_data[0]~reg0.CLK
clk => rx_data[1]~reg0.CLK
clk => rx_data[2]~reg0.CLK
clk => rx_data[3]~reg0.CLK
clk => rx_data[4]~reg0.CLK
clk => rx_data[5]~reg0.CLK
clk => rx_data[6]~reg0.CLK
clk => rx_data[7]~reg0.CLK
clk => rx_reg[0].CLK
clk => rx_reg[1].CLK
clk => rx_reg[2].CLK
clk => rx_reg[3].CLK
clk => rx_reg[4].CLK
clk => rx_reg[5].CLK
clk => rx_reg[6].CLK
clk => rx_reg[7].CLK
clk => rx_rdy~reg0.CLK
clk => rx_cnt[0].CLK
clk => rx_cnt[1].CLK
clk => rx_cnt[2].CLK
clk => rx_cnt[3].CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => count[5].CLK
clk => rx_state~5.DATAIN
rst_n => rx_data[0]~reg0.ACLR
rst_n => rx_data[1]~reg0.ACLR
rst_n => rx_data[2]~reg0.ACLR
rst_n => rx_data[3]~reg0.ACLR
rst_n => rx_data[4]~reg0.ACLR
rst_n => rx_data[5]~reg0.ACLR
rst_n => rx_data[6]~reg0.ACLR
rst_n => rx_data[7]~reg0.ACLR
rst_n => rx_reg[0].ACLR
rst_n => rx_reg[1].ACLR
rst_n => rx_reg[2].ACLR
rst_n => rx_reg[3].ACLR
rst_n => rx_reg[4].ACLR
rst_n => rx_reg[5].ACLR
rst_n => rx_reg[6].ACLR
rst_n => rx_reg[7].ACLR
rst_n => rx_rdy~reg0.ACLR
rst_n => rx_cnt[0].ACLR
rst_n => rx_cnt[1].ACLR
rst_n => rx_cnt[2].ACLR
rst_n => rx_cnt[3].ACLR
rst_n => count[0].ACLR
rst_n => count[1].ACLR
rst_n => count[2].ACLR
rst_n => count[3].ACLR
rst_n => count[4].ACLR
rst_n => count[5].ACLR
rst_n => rx_state~7.DATAIN
rx_en => count.OUTPUTSELECT
rx_en => count.OUTPUTSELECT
rx_en => count.OUTPUTSELECT
rx_en => count.OUTPUTSELECT
rx_en => count.OUTPUTSELECT
rx_en => count.OUTPUTSELECT
rx_en => rx_state.OUTPUTSELECT
rx_en => rx_state.OUTPUTSELECT
rx_en => rx_state.OUTPUTSELECT
rx_en => rx_state.OUTPUTSELECT
rx_en => rx_cnt.OUTPUTSELECT
rx_en => rx_cnt.OUTPUTSELECT
rx_en => rx_cnt.OUTPUTSELECT
rx_en => rx_cnt.OUTPUTSELECT
rx_en => rx_rdy.OUTPUTSELECT
rx_en => rx_reg.OUTPUTSELECT
rx_en => rx_reg.OUTPUTSELECT
rx_en => rx_reg.OUTPUTSELECT
rx_en => rx_reg.OUTPUTSELECT
rx_en => rx_reg.OUTPUTSELECT
rx_en => rx_reg.OUTPUTSELECT
rx_en => rx_reg.OUTPUTSELECT
rx_en => rx_reg.OUTPUTSELECT
rx_en => rx_data.OUTPUTSELECT
rx_en => rx_data.OUTPUTSELECT
rx_en => rx_data.OUTPUTSELECT
rx_en => rx_data.OUTPUTSELECT
rx_en => rx_data.OUTPUTSELECT
rx_en => rx_data.OUTPUTSELECT
rx_en => rx_data.OUTPUTSELECT
rx_en => rx_data.OUTPUTSELECT
rx_pin => rx_reg.DATAB
rx_pin => rx_reg.DATAB
rx_pin => rx_reg.DATAB
rx_pin => rx_reg.DATAB
rx_pin => rx_reg.DATAB
rx_pin => rx_reg.DATAB
rx_pin => rx_reg.DATAB
rx_pin => rx_reg.DATAB
rx_pin => rx_state.OUTPUTSELECT
rx_pin => rx_state.OUTPUTSELECT
rx_pin => rx_state.OUTPUTSELECT
rx_pin => rx_state.OUTPUTSELECT
rx_pin => count.OUTPUTSELECT
rx_pin => count.OUTPUTSELECT
rx_pin => count.OUTPUTSELECT
rx_pin => count.OUTPUTSELECT
rx_pin => count.OUTPUTSELECT
rx_pin => count.OUTPUTSELECT
rx_rdy <= rx_rdy~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data[0] <= rx_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data[1] <= rx_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data[2] <= rx_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data[3] <= rx_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data[4] <= rx_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data[5] <= rx_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data[6] <= rx_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data[7] <= rx_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE