57 lines
1.2 KiB
Coq
57 lines
1.2 KiB
Coq
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module uart_tx (
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input wire clk,
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input wire rst_n,
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input wire tx_en,
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input wire tx_start,
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input wire [7:0] tx_data,
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output reg uart_busy,
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output reg tx;
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);
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reg [7:0] tx_reg;
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reg [4:0] tx_cnt;
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always @(posedge clk or negedge rst_n or posedge tx_start) begin
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if (~rst_n) begin
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tx <= 1'b1;
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tx_reg <= 8'd0;
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tx_cnt <= 5'd0;
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uart_busy <= 1'b0;
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end
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else if(tx_start) begin
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if(tx_cnt == 0) begin
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tx_reg <= tx_data;
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tx_cnt <= 4'd10;
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uart_busy <= 1'b1;
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end
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else begin
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tx_cnt <= tx_cnt;
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end
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end
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else begin
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if(tx_cnt > 0) begin
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if(tx_cnt == 4'd10) begin
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tx <= 1'b0;
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end
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else if(tx_cnt > 4'd1) begin
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tx <= tx_reg[0];
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tx_reg <= tx_reg >> 1;
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end
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else begin
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tx <= 1'b1;
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end
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tx_cnt <= tx_cnt - 1;
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end
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else begin
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tx_cnt <= tx_cnt;
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tx <= 1'b1;
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uart_busy <= 1'b0;
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end
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end
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end
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endmodule //uart_tx
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