FPGA_module/uart/uart_top.v.bak

module uart_top(
    input wire clk,
    input wire rst_n,
    output wire tx
);

reg uart_tx_start;
reg [7:0] uart_tx_data;
wire uart_busy;

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        uart_tx_start <= 1'b0;
        uart_tx_data <= 8'd0;
    end
    else begin
        if(uart_busy == 1'b0) begin
            if(uart_tx_start == 1'b0) begin
                uart_tx_start <= 1'b1;
                uart_tx_data <= 8'd0;
                uart_tx_data <= uart_tx_data + 8'd1;
            end 
            else begin
                uart_tx_start <= uart_tx_start;
            end
        end
        else begin
            uart_tx_start <= 1'b0;
        end
    end
end


uart_tx uart_tx_tb0(
    .clk(clk),
    .rst_n(rst_n),
    .tx_en(1'b1),
    .tx_start(uart_tx_start),
    .tx_data(uart_tx_data),
    .uart_busy(uart_busy),
    .tx(tx)
);

endmodule