84 lines
1.5 KiB
Coq
84 lines
1.5 KiB
Coq
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`timescale 1ns/1ps
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module clk_tb;
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reg clk, rst_n;
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initial begin
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clk = 0;
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end
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always #1 clk = ~clk;
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initial begin
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rst_n = 1;
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#1 rst_n = 0;
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#1 rst_n = 1;
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end
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// module uart_top(
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// input wire clk,
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// input wire rst_n,
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// output wire clk_uart_tx,
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// output wire tx_pin,
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// output wire tx_busy,
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// input wire rx_pin,
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// output wire[7:0] rx_data;
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// output wire rx_rdy;
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// );
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wire clk_uart_tx;
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wire tx_pin;
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wire tx_busy;
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reg rx_pin;
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wire[7:0] rx_data;
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wire rx_rdy;
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uart_top uart_top_inst(
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.clk(clk),
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.rst_n(rst_n),
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.clk_uart_tx(clk_uart_tx),
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.tx_pin(tx_pin),
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.tx_busy(tx_busy),
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.rx_pin(rx_pin),
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.rx_data(rx_data),
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.rx_rdy(rx_rdy)
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);
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reg [7:0] tx_data;
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initial begin
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rx_pin = 1;
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#10;
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tx_data = 8'h55;
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rx_pin = 1'b0;#200;
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rx_pin = tx_data[0] ;#200;
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rx_pin = tx_data[1] ;#200;
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rx_pin = tx_data[2] ;#200;
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rx_pin = tx_data[3] ;#200;
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rx_pin = tx_data[4] ;#200;
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rx_pin = tx_data[5] ;#200;
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rx_pin = tx_data[6] ;#200;
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rx_pin = tx_data[7] ;#200;
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rx_pin = 1'b1 ;#200;
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// #200;
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tx_data = 8'hAA;
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rx_pin = 1'b0 ;#200;
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rx_pin = tx_data[0] ;#200;
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rx_pin = tx_data[1] ;#200;
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rx_pin = tx_data[2] ;#200;
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rx_pin = tx_data[3] ;#200;
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rx_pin = tx_data[4] ;#200;
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rx_pin = tx_data[5] ;#200;
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rx_pin = tx_data[6] ;#200;
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rx_pin = tx_data[7] ;#200;
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rx_pin = 1'b1 ;#200;
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#200;
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end
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initial begin
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$dumpfile("uart_tb.vcd");
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$dumpvars(0, clk_tb);
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#100000 $finish;
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end
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endmodule
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