83 lines
2.0 KiB
Coq
83 lines
2.0 KiB
Coq
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module uart_rx(
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input wire clk,
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input wire rst_n,
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input wire rx_en,
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input wire rx,
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output wire rx_rdy,
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output wire [7:0] rx_data
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);
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reg [7:0] rx_reg;
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reg [4:0] rx_cnt;
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reg [1:0] state;
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reg [1:0] state_next;
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parameter STOP = 2'd0, IDLE = 2'd1, DATA = 2'd2;
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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state <= STOP;
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end
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else begin
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state <= state_next;
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end
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end
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always @( *) begin
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if(rx_en == 1'd0) begin
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state_next = STOP;
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end
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else begin
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case(state)
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default state_next <= state_next;
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STOP: state_next <= IDLE;
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IDLE: begin
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if(rx == 1'd0) state_next <= DATA;
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else state_next <= IDLE;
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end
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DATA: begin
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if(rx_cnt == 5'd10) state_next <= IDLE;
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else state_next <= DATA;
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end
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endcase
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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rx_rdy <= 1'd0;
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rx_data <= 8'd0;
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rx_cnt <= 5'd0;
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end
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else begin
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case(state)
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default rx_rdy <= 1'd0;
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STOP: begin
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rx_rdy <= 1'd0;
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rx_data <= 8'd0;
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rx_cnt <= 5'd0;
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end
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IDLE : begin
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rx_rdy <= rx_rdy;
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rx_data <= 8'd0;
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rx_cnt <= 5'd0;
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end
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DATA: begin
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if(rx_cnt == 5'd0) begin
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rx_cnt <= rx_cnt + 1'd1;
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end
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else if (rx_cnt < 5'd9) begin
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rx_reg[rx_cnt-1'd1] <= rx;
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rx_cnt <= rx_cnt + 1'd1;
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end
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else if (rx_cnt == 5'd9) begin
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rx_cnt <= rx_cnt + 1'd1;
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rx_rdy <= 1'd1;
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end
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else begin
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rx_rdy <= 1'd1;
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end
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end
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endcase
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end
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end
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endmodule
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