FPGA_util
/
FPGA_module
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
FPGA_module/uart/par/db/excute.fit.qmsg

52 lines
31 KiB
Plaintext
Raw Normal View History

1
2024-08-04 06:24:44 +00:00
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1722731686072 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "excute EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"excute\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1722731686083 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1722731686115 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1722731686115 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1722731686115 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1722731686169 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1722731686427 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1722731686427 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1722731686427 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1722731686427 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 196 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722731686434 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 198 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722731686434 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 200 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722731686434 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 202 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722731686434 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 204 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1722731686434 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1722731686434 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1722731686437 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "3 15 " "No exact pin location assignment(s) for 3 pins of 15 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_uart_tx " "Pin clk_uart_tx not assigned to an exact location on the device" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { clk_uart_tx } } } { "../uart_top.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_top.v" 4 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_uart_tx } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 17 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1722731686764 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "tx_busy " "Pin tx_busy not assigned to an exact location on the device" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { tx_busy } } } { "../uart_top.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_top.v" 6 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { tx_busy } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 19 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1722731686764 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rx_rdy " "Pin rx_rdy not assigned to an exact location on the device" { } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { rx_rdy } } } { "../uart_top.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_top.v" 10 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { rx_rdy } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 21 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1722731686764 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1722731686764 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "8 " "TimeQuest Timing Analyzer is analyzing 8 combinational loops as latches." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Fitter" 0 -1 1722731686946 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "excute.sdc " "Synopsys Design Constraints File file not found: 'excute.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1722731686947 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1722731686948 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1722731686949 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1722731686949 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1722731686951 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1722731686959 ""} } { { "../uart_top.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_top.v" 2 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 189 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1722731686959 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "div_clk:uart_div_c0\|clk_div " "Automatically promoted node div_clk:uart_div_c0\|clk_div " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1722731686959 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "div_clk:uart_div_c0\|clk_div~0 " "Destination node div_clk:uart_div_c0\|clk_div~0" { } { { "../div_clk.v" "" { Text "E:/FPGA/FPGA_lib/uart/div_clk.v" 1 -1 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { div_clk:uart_div_c0|clk_div~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 109 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1722731686959 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_uart_tx~output " "Destination node clk_uart_tx~output" { } { { "../uart_top.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_top.v" 4 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_uart_tx~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 177 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1722731686959 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1722731686959 ""} } { { "../div_clk.v" "" { Text "E:/FPGA/FPGA_lib/uart/div_clk.v" 1 -1 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { div_clk:uart_div_c0|clk_div } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 89 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1722731686959 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "uart_rx:uart_rx_c0\|rx_rdy " "Automatically promoted node uart_rx:uart_rx_c0\|rx_rdy " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1722731686960 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_rdy~output " "Destination node rx_rdy~output" { } { { "../uart_top.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_top.v" 10 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { rx_rdy~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 188 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1722731686960 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1722731686960 ""} } { { "../uart_rx.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_rx.v" 6 -1 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { uart_rx:uart_rx_c0|rx_rdy } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 50 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1722731686960 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "uart_tx:uart_tx_c0\|state.STA_IDLE " "Automatically promoted node uart_tx:uart_tx_c0\|state.STA_IDLE " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1722731686960 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "uart_tx:uart_tx_c0\|Selector2~1 " "Destination node uart_tx:uart_tx_c0\|Selector2~1" { } { { "../uart_tx.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_tx.v" 24 -1 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { uart_tx:uart_tx_c0|Selector2~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 121 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1722731686960 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1722731686960 ""} } { { "../uart_tx.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_tx.v" 11 -1 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { uart_tx:uart_tx_c0|state.STA_IDLE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 69 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1722731686960 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN M1 (CLK3, DIFFCLK_1n)) " "Automatically promoted node rst_n~input (placed in PIN M1 (CLK3, DIFFCLK_1n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1722731686960 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "send_flag~0 " "Destination node send_flag~0" { } { { "../uart_top.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_top.v" 25 -1 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { send_flag~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1722731686960 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1722731686960 ""} } { { "../uart_top.v" "" { Text "E:/FPGA/FPGA_lib/uart/uart_top.v" 3 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { rst_n~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 0 { 0 ""} 0 190 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1722731686960 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1722731687176 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1722731687177 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1722731687177 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1722731687177 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1722731687178 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1722731687178 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1722731687178 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1722731687178 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1722731687383 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1722731687384 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1722731687384 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 2.5V 0 3 0 " "Number of I/O pins in group: 3 (unused VREF, 2.5V VCCIO, 0 input, 3 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1722731687387 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1722731687387 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1722731687387 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 12 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1722731687387 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 18 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1722731687387 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 26 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1722731687387 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 27 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1722731687387 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 25 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1722731687387 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 13 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1722731687387 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 3 23 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 3 total pin(s) used -- 23 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1722731687387 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 2.5V 7 19 " "I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 7 total pin(s) used -- 19 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1722731687387 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1722731687387 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1722731687387 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722731687402 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1722731687830 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722731687889 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1722731687898 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1722731688412 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722731688412 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1722731688625 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" { } { { "loc" "" { Generic "E:/FPGA/FPGA_lib/uart/par/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} 11 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1722731688986 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1722731688986 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722731689363 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1722731689364 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1722731689364 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1722731689372 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1722731689420 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1722731689535 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1722731689577 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1722731689703 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1722731689975 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/FPGA_lib/uart/par/output_files/excute.fit.smsg " "Generated suppressed messages file E:/FPGA/FPGA_lib/uart/par/output_files/excute.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1722731690288 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5880 " "Peak virtual memory: 5880 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1722731690540 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 04 08:34:50 2024 " "Processing ended: Sun Aug 04 08:34:50 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1722731690540 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1722731690540 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1722731690540 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1722731690540 ""}