69 lines
3.2 KiB
Plaintext
69 lines
3.2 KiB
Plaintext
|
# -------------------------------------------------------------------------- #
|
||
|
|
#
|
||
|
|
# Copyright (C) 1991-2013 Altera Corporation
|
||
|
|
# Your use of Altera Corporation's design tools, logic functions
|
||
|
|
# and other software and tools, and its AMPP partner logic
|
||
|
|
# functions, and any output files from any of the foregoing
|
||
|
|
# (including device programming or simulation files), and any
|
||
|
|
# associated documentation or information are expressly subject
|
||
|
|
# to the terms and conditions of the Altera Program License
|
||
|
|
# Subscription Agreement, Altera MegaCore Function License
|
||
|
|
# Agreement, or other applicable license agreement, including,
|
||
|
|
# without limitation, that your use is for the sole purpose of
|
||
|
|
# programming logic devices manufactured by Altera and sold by
|
||
|
|
# Altera or its authorized distributors. Please refer to the
|
||
|
|
# applicable agreement for further details.
|
||
|
|
#
|
||
|
|
# -------------------------------------------------------------------------- #
|
||
|
|
#
|
||
|
|
# Quartus II 64-Bit
|
||
|
|
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||
|
|
# Date created = 00:02:45 August 03, 2024
|
||
|
|
#
|
||
|
|
# -------------------------------------------------------------------------- #
|
||
|
|
#
|
||
|
|
# Notes:
|
||
|
|
#
|
||
|
|
# 1) The default values for assignments are stored in the file:
|
||
|
|
# test_assignment_defaults.qdf
|
||
|
|
# If this file doesn't exist, see file:
|
||
|
|
# assignment_defaults.qdf
|
||
|
|
#
|
||
|
|
# 2) Altera recommends that you do not modify this file. This
|
||
|
|
# file is updated automatically by the Quartus II software
|
||
|
|
# and any changes you make may be lost or overwritten.
|
||
|
|
#
|
||
|
|
# -------------------------------------------------------------------------- #
|
||
|
|
|
||
|
|
|
||
|
|
set_global_assignment -name FAMILY "Cyclone IV E"
|
||
|
|
set_global_assignment -name DEVICE EP4CE10F17C8
|
||
|
|
set_global_assignment -name TOP_LEVEL_ENTITY test_top
|
||
|
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||
|
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:02:45 AUGUST 03, 2024"
|
||
|
|
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||
|
|
set_global_assignment -name VERILOG_FILE ../test_top.v
|
||
|
|
set_global_assignment -name VERILOG_FILE ../div_clk.v
|
||
|
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||
|
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||
|
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||
|
|
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
|
||
|
|
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
|
||
|
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||
|
|
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||
|
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||
|
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||
|
|
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
|
||
|
|
set_location_assignment PIN_A2 -to a2
|
||
|
|
set_location_assignment PIN_A3 -to a3
|
||
|
|
set_location_assignment PIN_A4 -to a4
|
||
|
|
set_location_assignment PIN_A5 -to a5
|
||
|
|
set_location_assignment PIN_A6 -to a6
|
||
|
|
set_location_assignment PIN_A7 -to a7
|
||
|
|
set_location_assignment PIN_A8 -to a8
|
||
|
|
set_location_assignment PIN_A9 -to a9
|
||
|
|
set_location_assignment PIN_E1 -to clk
|
||
|
|
set_location_assignment PIN_M1 -to rst_n
|
||
|
|
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
|
||
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|