22 lines
350 B
Coq
22 lines
350 B
Coq
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module clk_test (
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input wire clk,
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input wire rst_n
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);
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reg clk_out;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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clk_out <= 0;
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end else begin
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if (clk_out == 1'b0) begin
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clk_out <= 1'b1;
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end else begin
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clk_out <= 1'b0;
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end
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end
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end
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endmodule //clk_test
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