FPGA_module/clk/clk_tb.vcd

$date
	Tue Jul 30 20:27:09 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module clk_tb $end
$var wire 1 ! rst $end
$var reg 1 " clk $end
$var reg 1 # rst_n $end
$scope module tb_clk $end
$var wire 1 " clk $end
$var wire 1 ! rst_n $end
$var reg 1 $ clk_out $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
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$dumpvars
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