FPGA_module/uart/out

#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "D:\GNU\iverilog\lib\ivl\system.vpi";
:vpi_module "D:\GNU\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "D:\GNU\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "D:\GNU\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "D:\GNU\iverilog\lib\ivl\va_math.vpi";
S_000001bf75905740 .scope module, "clk_tb" "clk_tb" 2 4;
 .timescale -9 -12;
P_000001bf758d1b40 .param/l "delay" 0 2 32, +C4<00000000000000000000000001100100>;
v000001bf7595fbc0_0 .var "clk", 0 0;
v000001bf7595fd00_0 .var "rst_n", 0 0;
v000001bf75960ef0_0 .var "rx_pin", 0 0;
v000001bf759603b0_0 .var "tx_data", 7 0;
S_000001bf755c6790 .scope module, "uart_top_inst" "uart_top" 2 27, 3 1 0, S_000001bf75905740;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rstn";
    .port_info 2 /INPUT 1 "rx_pin";
    .port_info 3 /OUTPUT 1 "tx_pin";
v000001bf7595f800_0 .net "clk", 0 0, v000001bf7595fbc0_0;  1 drivers
v000001bf7595f8a0_0 .net "rstn", 0 0, v000001bf7595fd00_0;  1 drivers
v000001bf7595f4e0_0 .net "rx_data", 7 0, v000001bf759052c0_0;  1 drivers
v000001bf7595f1c0_0 .net "rx_pin", 0 0, v000001bf75960ef0_0;  1 drivers
v000001bf7595fee0_0 .net "rx_rdy", 0 0, v000001bf755c6920_0;  1 drivers
v000001bf7595f580_0 .var "state", 2 0;
v000001bf7595f080_0 .net "tx_busy", 0 0, v000001bf7595f9e0_0;  1 drivers
v000001bf7595f260_0 .var "tx_data", 7 0;
v000001bf7595fe40_0 .net "tx_pin", 0 0, v000001bf7595fc60_0;  1 drivers
v000001bf7595f940_0 .net "tx_ply_ok", 0 0, v000001bf7595f760_0;  1 drivers
v000001bf7595fb20_0 .var "tx_req_start", 0 0;
S_000001bf758eadc0 .scope module, "uart_rx_c0" "uart_rx" 3 25, 4 1 0, S_000001bf755c6790;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "rx_en";
    .port_info 3 /INPUT 1 "rx_pin";
    .port_info 4 /OUTPUT 1 "rx_rdy";
    .port_info 5 /OUTPUT 8 "rx_data";
P_000001bf755c7080 .param/l "COUNT_WITH" 0 4 11, +C4<00000000000000000000000000000110>;
P_000001bf755c70b8 .param/l "DIV" 0 4 10, +C4<00000000000000000000000000110010>;
v000001bf755cbc80_0 .net "clk", 0 0, v000001bf7595fbc0_0;  alias, 1 drivers
v000001bf759058d0_0 .var "count", 5 0;
v000001bf75905f20_0 .net "rst_n", 0 0, v000001bf7595fd00_0;  alias, 1 drivers
v000001bf75905500_0 .var "rx_cnt", 3 0;
v000001bf759052c0_0 .var "rx_data", 7 0;
L_000001bf75cd00d0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v000001bf758ce3f0_0 .net "rx_en", 0 0, L_000001bf75cd00d0;  1 drivers
v000001bf758ce490_0 .net "rx_pin", 0 0, v000001bf75960ef0_0;  alias, 1 drivers
v000001bf755c6920_0 .var "rx_rdy", 0 0;
v000001bf755c69c0_0 .var "rx_reg", 7 0;
v000001bf758eaf50_0 .var "rx_state", 1 0;
E_000001bf758d10c0/0 .event negedge, v000001bf75905f20_0;
E_000001bf758d10c0/1 .event posedge, v000001bf755cbc80_0;
E_000001bf758d10c0 .event/or E_000001bf758d10c0/0, E_000001bf758d10c0/1;
S_000001bf758eaff0 .scope module, "uart_tx_c0" "uart_tx" 3 12, 5 1 0, S_000001bf755c6790;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rstn";
    .port_info 2 /INPUT 1 "en";
    .port_info 3 /INPUT 1 "tx_req_start";
    .port_info 4 /INPUT 8 "tx_data";
    .port_info 5 /OUTPUT 1 "tx_ply_ok";
    .port_info 6 /OUTPUT 1 "tx_busy";
    .port_info 7 /OUTPUT 1 "tx_pin";
P_000001bf75905360 .param/l "COUNT_WITH" 0 5 13, +C4<00000000000000000000000000000110>;
P_000001bf75905398 .param/l "DIV" 0 5 12, +C4<00000000000000000000000000110010>;
v000001bf7595fa80_0 .net "clk", 0 0, v000001bf7595fbc0_0;  alias, 1 drivers
v000001bf7595ff80_0 .var "count", 5 0;
v000001bf7595fda0_0 .var "data_reg", 7 0;
L_000001bf75cd0088 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v000001bf7595f300_0 .net "en", 0 0, L_000001bf75cd0088;  1 drivers
v000001bf7595f620_0 .net "rstn", 0 0, v000001bf7595fd00_0;  alias, 1 drivers
v000001bf7595f3a0_0 .var "state", 2 0;
v000001bf7595f9e0_0 .var "tx_busy", 0 0;
v000001bf7595f6c0_0 .var "tx_count", 3 0;
v000001bf7595f120_0 .net "tx_data", 7 0, v000001bf7595f260_0;  1 drivers
v000001bf7595fc60_0 .var "tx_pin", 0 0;
v000001bf7595f760_0 .var "tx_ply_ok", 0 0;
v000001bf7595f440_0 .net "tx_req_start", 0 0, v000001bf7595fb20_0;  1 drivers
S_000001bf755c6600 .scope module, "div_clk" "div_clk" 6 1;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rstn";
    .port_info 2 /OUTPUT 1 "clk_div";
P_000001bf755c6c40 .param/l "COUNT_WITH" 0 6 4, +C4<00000000000000000000000000001010>;
P_000001bf755c6c78 .param/l "DIV" 0 6 3, +C4<00000000000000000000000000001010>;
o000001bf75908768 .functor BUFZ 1, C4<z>; HiZ drive
v000001bf75960310_0 .net "clk", 0 0, o000001bf75908768;  0 drivers
v000001bf75960450_0 .var "clk_div", 0 0;
v000001bf75960090_0 .var "count", 9 0;
o000001bf759087f8 .functor BUFZ 1, C4<z>; HiZ drive
v000001bf759604f0_0 .net "rstn", 0 0, o000001bf759087f8;  0 drivers
E_000001bf758d1980/0 .event negedge, v000001bf759604f0_0;
E_000001bf758d1980/1 .event posedge, v000001bf75960310_0;
E_000001bf758d1980 .event/or E_000001bf758d1980/0, E_000001bf758d1980/1;
    .scope S_000001bf758eaff0;
T_0 ;
    %wait E_000001bf758d10c0;
    %load/vec4 v000001bf7595f620_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_0.0, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001bf7595fc60_0, 0;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001bf7595ff80_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001bf7595f6c0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001bf7595f3a0_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001bf7595fda0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf7595f760_0, 0;
    %jmp T_0.1;
T_0.0 ;
    %load/vec4 v000001bf7595f300_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_0.2, 4;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001bf7595fc60_0, 0;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001bf7595ff80_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001bf7595f6c0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001bf7595f3a0_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001bf7595fda0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf7595f760_0, 0;
    %jmp T_0.3;
T_0.2 ;
    %load/vec4 v000001bf7595f3a0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 3;
    %cmp/u;
    %jmp/1 T_0.4, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 3;
    %cmp/u;
    %jmp/1 T_0.5, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 3;
    %cmp/u;
    %jmp/1 T_0.6, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 3;
    %cmp/u;
    %jmp/1 T_0.7, 6;
    %jmp T_0.8;
T_0.4 ;
    %load/vec4 v000001bf7595f440_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_0.9, 8;
    %load/vec4 v000001bf7595f120_0;
    %assign/vec4 v000001bf7595fda0_0, 0;
    %pushi/vec4 1, 0, 3;
    %assign/vec4 v000001bf7595f3a0_0, 0;
T_0.9 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf7595f760_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001bf7595fc60_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001bf7595f6c0_0, 0;
    %jmp T_0.8;
T_0.5 ;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001bf7595f760_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf7595fc60_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001bf7595f6c0_0, 0;
    %load/vec4 v000001bf7595ff80_0;
    %pad/u 32;
    %cmpi/e 49, 0, 32;
    %jmp/0xz  T_0.11, 4;
    %pushi/vec4 2, 0, 3;
    %assign/vec4 v000001bf7595f3a0_0, 0;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001bf7595ff80_0, 0;
    %jmp T_0.12;
T_0.11 ;
    %load/vec4 v000001bf7595ff80_0;
    %addi 1, 0, 6;
    %assign/vec4 v000001bf7595ff80_0, 0;
T_0.12 ;
    %jmp T_0.8;
T_0.6 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf7595f760_0, 0;
    %load/vec4 v000001bf7595fda0_0;
    %load/vec4 v000001bf7595f6c0_0;
    %part/u 1;
    %assign/vec4 v000001bf7595fc60_0, 0;
    %load/vec4 v000001bf7595ff80_0;
    %pad/u 32;
    %cmpi/e 49, 0, 32;
    %jmp/0xz  T_0.13, 4;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001bf7595ff80_0, 0;
    %load/vec4 v000001bf7595f6c0_0;
    %addi 1, 0, 4;
    %assign/vec4 v000001bf7595f6c0_0, 0;
    %jmp T_0.14;
T_0.13 ;
    %load/vec4 v000001bf7595ff80_0;
    %addi 1, 0, 6;
    %assign/vec4 v000001bf7595ff80_0, 0;
T_0.14 ;
    %load/vec4 v000001bf7595f6c0_0;
    %pad/u 32;
    %cmpi/e 8, 0, 32;
    %jmp/0xz  T_0.15, 4;
    %pushi/vec4 3, 0, 3;
    %assign/vec4 v000001bf7595f3a0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001bf7595fc60_0, 0;
T_0.15 ;
    %jmp T_0.8;
T_0.7 ;
    %load/vec4 v000001bf7595ff80_0;
    %pad/u 32;
    %cmpi/e 49, 0, 32;
    %jmp/0xz  T_0.17, 4;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001bf7595ff80_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001bf7595f3a0_0, 0;
    %jmp T_0.18;
T_0.17 ;
    %load/vec4 v000001bf7595ff80_0;
    %addi 1, 0, 6;
    %assign/vec4 v000001bf7595ff80_0, 0;
T_0.18 ;
    %jmp T_0.8;
T_0.8 ;
    %pop/vec4 1;
T_0.3 ;
T_0.1 ;
    %jmp T_0;
    .thread T_0;
    .scope S_000001bf758eadc0;
T_1 ;
    %wait E_000001bf758d10c0;
    %load/vec4 v000001bf75905f20_0;
    %inv;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.0, 8;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001bf759058d0_0, 0;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001bf758eaf50_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001bf75905500_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf755c6920_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001bf755c69c0_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001bf759052c0_0, 0;
    %jmp T_1.1;
T_1.0 ;
    %load/vec4 v000001bf758ce3f0_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_1.2, 4;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001bf759058d0_0, 0;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001bf758eaf50_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001bf75905500_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf755c6920_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001bf755c69c0_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001bf759052c0_0, 0;
    %jmp T_1.3;
T_1.2 ;
    %load/vec4 v000001bf758eaf50_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 2;
    %cmp/u;
    %jmp/1 T_1.4, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 2;
    %cmp/u;
    %jmp/1 T_1.5, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 2;
    %cmp/u;
    %jmp/1 T_1.6, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 2;
    %cmp/u;
    %jmp/1 T_1.7, 6;
    %jmp T_1.8;
T_1.4 ;
    %load/vec4 v000001bf758ce490_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_1.9, 4;
    %pushi/vec4 1, 0, 2;
    %assign/vec4 v000001bf758eaf50_0, 0;
    %pushi/vec4 1, 0, 6;
    %assign/vec4 v000001bf759058d0_0, 0;
T_1.9 ;
    %jmp T_1.8;
T_1.5 ;
    %load/vec4 v000001bf759058d0_0;
    %pad/u 32;
    %cmpi/e 49, 0, 32;
    %jmp/0xz  T_1.11, 4;
    %pushi/vec4 2, 0, 2;
    %assign/vec4 v000001bf758eaf50_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000001bf75905500_0, 0;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001bf759058d0_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001bf755c69c0_0, 0;
    %jmp T_1.12;
T_1.11 ;
    %load/vec4 v000001bf759058d0_0;
    %addi 1, 0, 6;
    %assign/vec4 v000001bf759058d0_0, 0;
T_1.12 ;
    %jmp T_1.8;
T_1.6 ;
    %load/vec4 v000001bf759058d0_0;
    %pad/u 32;
    %cmpi/e 49, 0, 32;
    %jmp/0xz  T_1.13, 4;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001bf759058d0_0, 0;
    %load/vec4 v000001bf75905500_0;
    %pad/u 32;
    %cmpi/e 8, 0, 32;
    %jmp/0xz  T_1.15, 4;
    %pushi/vec4 3, 0, 2;
    %assign/vec4 v000001bf758eaf50_0, 0;
T_1.15 ;
    %jmp T_1.14;
T_1.13 ;
    %load/vec4 v000001bf759058d0_0;
    %pad/u 32;
    %cmpi/e 24, 0, 32;
    %jmp/0xz  T_1.17, 4;
    %load/vec4 v000001bf758ce490_0;
    %ix/load 5, 0, 0;
    %ix/getv 4, v000001bf75905500_0;
    %assign/vec4/off/d v000001bf755c69c0_0, 4, 5;
    %load/vec4 v000001bf75905500_0;
    %addi 1, 0, 4;
    %assign/vec4 v000001bf75905500_0, 0;
    %load/vec4 v000001bf759058d0_0;
    %addi 1, 0, 6;
    %assign/vec4 v000001bf759058d0_0, 0;
    %jmp T_1.18;
T_1.17 ;
    %load/vec4 v000001bf759058d0_0;
    %addi 1, 0, 6;
    %assign/vec4 v000001bf759058d0_0, 0;
T_1.18 ;
T_1.14 ;
    %jmp T_1.8;
T_1.7 ;
    %load/vec4 v000001bf759058d0_0;
    %pad/u 32;
    %cmpi/e 49, 0, 32;
    %jmp/0xz  T_1.19, 4;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001bf759058d0_0, 0;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001bf758eaf50_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf755c6920_0, 0;
    %jmp T_1.20;
T_1.19 ;
    %load/vec4 v000001bf759058d0_0;
    %addi 1, 0, 6;
    %assign/vec4 v000001bf759058d0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001bf755c6920_0, 0;
    %load/vec4 v000001bf755c69c0_0;
    %assign/vec4 v000001bf759052c0_0, 0;
T_1.20 ;
    %jmp T_1.8;
T_1.8 ;
    %pop/vec4 1;
T_1.3 ;
T_1.1 ;
    %jmp T_1;
    .thread T_1;
    .scope S_000001bf755c6790;
T_2 ;
    %wait E_000001bf758d10c0;
    %load/vec4 v000001bf7595f8a0_0;
    %inv;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.0, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001bf7595f580_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf7595fb20_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000001bf7595f260_0, 0;
    %jmp T_2.1;
T_2.0 ;
    %load/vec4 v000001bf7595f580_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 3;
    %cmp/u;
    %jmp/1 T_2.2, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 3;
    %cmp/u;
    %jmp/1 T_2.3, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 3;
    %cmp/u;
    %jmp/1 T_2.4, 6;
    %jmp T_2.5;
T_2.2 ;
    %load/vec4 v000001bf7595fee0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.6, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001bf7595fb20_0, 0;
    %load/vec4 v000001bf7595f4e0_0;
    %assign/vec4 v000001bf7595f260_0, 0;
    %pushi/vec4 1, 0, 3;
    %assign/vec4 v000001bf7595f580_0, 0;
T_2.6 ;
    %jmp T_2.5;
T_2.3 ;
    %load/vec4 v000001bf7595f940_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.8, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf7595fb20_0, 0;
    %pushi/vec4 2, 0, 3;
    %assign/vec4 v000001bf7595f580_0, 0;
T_2.8 ;
    %jmp T_2.5;
T_2.4 ;
    %load/vec4 v000001bf7595f940_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_2.10, 4;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v000001bf7595f580_0, 0;
T_2.10 ;
    %jmp T_2.5;
T_2.5 ;
    %pop/vec4 1;
T_2.1 ;
    %jmp T_2;
    .thread T_2;
    .scope S_000001bf75905740;
T_3 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bf7595fbc0_0, 0, 1;
    %end;
    .thread T_3;
    .scope S_000001bf75905740;
T_4 ;
    %delay 1000, 0;
    %load/vec4 v000001bf7595fbc0_0;
    %inv;
    %store/vec4 v000001bf7595fbc0_0, 0, 1;
    %jmp T_4;
    .thread T_4;
    .scope S_000001bf75905740;
T_5 ;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bf7595fd00_0, 0, 1;
    %delay 1000, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bf7595fd00_0, 0, 1;
    %delay 1000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bf7595fd00_0, 0, 1;
    %end;
    .thread T_5;
    .scope S_000001bf75905740;
T_6 ;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 10000, 0;
    %pushi/vec4 85, 0, 8;
    %store/vec4 v000001bf759603b0_0, 0, 8;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 0, 2;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 1, 2;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 2, 3;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 3, 3;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 4, 4;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 5, 4;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 6, 4;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 7, 4;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %pushi/vec4 170, 0, 8;
    %store/vec4 v000001bf759603b0_0, 0, 8;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 0, 2;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 1, 2;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 2, 3;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 3, 3;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 4, 4;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 5, 4;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 6, 4;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %load/vec4 v000001bf759603b0_0;
    %parti/s 1, 7, 4;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bf75960ef0_0, 0, 1;
    %delay 100000, 0;
    %delay 100000, 0;
    %end;
    .thread T_6;
    .scope S_000001bf75905740;
T_7 ;
    %vpi_call 2 63 "$dumpfile", "uart_tb.vcd" {0 0 0};
    %vpi_call 2 64 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001bf75905740 {0 0 0};
    %delay 100000000, 0;
    %vpi_call 2 65 "$finish" {0 0 0};
    %end;
    .thread T_7;
    .scope S_000001bf755c6600;
T_8 ;
    %wait E_000001bf758d1980;
    %load/vec4 v000001bf759604f0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_8.0, 8;
    %pushi/vec4 0, 0, 10;
    %assign/vec4 v000001bf75960090_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001bf75960450_0, 0;
    %jmp T_8.1;
T_8.0 ;
    %load/vec4 v000001bf75960090_0;
    %pad/u 32;
    %cmpi/e 9, 0, 32;
    %jmp/0xz  T_8.2, 4;
    %pushi/vec4 0, 0, 10;
    %assign/vec4 v000001bf75960090_0, 0;
    %load/vec4 v000001bf75960450_0;
    %inv;
    %assign/vec4 v000001bf75960450_0, 0;
    %jmp T_8.3;
T_8.2 ;
    %load/vec4 v000001bf75960090_0;
    %addi 1, 0, 10;
    %assign/vec4 v000001bf75960090_0, 0;
T_8.3 ;
T_8.1 ;
    %jmp T_8;
    .thread T_8;
# The file index is used to find the file name in the following table.
:file_names 7;
    "N/A";
    "<interactive>";
    "uart_tb.v";
    "uart_top.v";
    "uart_rx.v";
    "uart_tx.v";
    "div_clk.v";