FPGA_module/uart/div_clk.v

module div_clk(input clk, rstn, output reg clk_div);

parameter DIV = 10;
parameter COUNT_WITH = 10;
reg [COUNT_WITH-1:0] count;

always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        count <= 0;
        clk_div <= 0;
    end else begin
        if (count == (DIV-1)) begin
            count <= 0;
            clk_div <= ~clk_div;
        end else begin
            count <= count + 1'd1;
        end 
    end
end

endmodule