FPGA_module/test/div_clk.v

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2024-08-04 06:24:44 +00:00
module div_clk(input clk, rst_n, output reg clk_div);
parameter DIV = 10;
parameter COUNT_WITH = 10;
reg [COUNT_WITH-1:0] count;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count <= 0;
clk_div <= 0;
end else begin
if (count == (DIV-1)) begin
count <= 0;
clk_div <= ~clk_div;
end else begin
count <= count + 1'd1;
end
end
end
endmodule